A digital image output apparatus such as a digital color copier reads an image as data of R (red), G (green), and B (blue) via a reading unit of this apparatus. The digital image output apparatus outputs this data as the data of C (cyan), M (magenta), and Y (yellow) to a printing unit of this apparatus. Accordingly, in the image processing of the digital image output apparatus, coordinate conversion from a RGB color space to a CMY color space is performed on the image data. In this coordinate conversion process, it is necessary to take into account an input property of a scanner and an output property of a plotter, and converted coordinate values cannot be calculated in a simple manner. Conventionally, a three-dimensional lookup table (hereinbelow, referred to as LUT) is used. However, depending on a bit width of RGB data, a large capacity can be required to configure the LUT. For example, when R data, G data, and B data is represented by the widths of 8 bits, respectively, the bits of 28×28×28 are required for the capacity of the LUT.
Conventionally, in order to reduce the capacity of the LUT, the color conversion process is performed as follows. A conventional configuration of a color conversion processing unit 90 is schematically shown in FIG. 15. This color conversion processing unit 90 includes a color conversion data memory area 91, and a correcting operation unit 92. C data, M data, and Y data that is formed by the upper 4 bits of R is written as addresses in the color conversion memory region in advance. C data, M data, and Y data that is formed by the upper 4 bits of G is written as addresses in the color conversion memory region in advance. C data, M data, and Y data that is formed by the upper 4 bits of B is written as addresses in the color conversion data memory area 91 in advance. As shown in FIG. 15, the three color conversion processing units 90 are prepared for the conversion to C data, the conversion to M data, and the conversion to Y data, respectively. Accordingly, the three color conversion data memory areas 91 in the respective color conversion processing units 90 correspond to the respective LUTs for the conversion to C data, the conversion to M data, and the conversion to Y data, respectively.
The upper 4-bit R data, the upper 4-bit G data, and the upper 4-bit B data out of the binary digit data of 8 bits read by a scanner (not shown) are used to read the data by using color conversion data memory areas 91. That is, at this time, one of the read data corresponds to a base address specified by the upper 4-bit data of R, G, and B, and the others of the read data correspond to predetermined addresses that are selected based on the base address. FIG. 16 shows one example of a plurality of addresses that are selected based on the base address (z, y, x) and are used for the data reading process.
When accessing a cyan memory area based on the base address (z, y, x) that is specified by the upper 4-bit data of R, G, and B, the base address indicated by “0” of FIG. 16 is selected, and a plurality of addresses (indicated by {circle around (1)} through {circle around (7)} of FIG. 16 that are determined by adding “1” to one, two, and all of x, y, and z constituting the base address are selected. In other words, 8 addresses including the base address (z, y, x) that define one cube, for example, are selected, as shown in FIG. 16. The data that corresponds to the selected plural addresses is read from the cyan memory area. This read data is rough information because the read data is based on the upper 4-bit data of R data, G data, and B data.
Thereafter, in order to obtain fine information, the lower 4-bit data of R data, G data, and B data is used. The correcting operation unit 92 performs a correcting arithmetic operation by using the data. In this manner, the fine information about the cyan data that is included in the cube of FIG. 16 defined by the eight addresses can be obtained, and the data on which the color conversion is performed can be extracted.
In the same manner of obtaining the cyan data, the color conversion processing units 90 perform the color conversion process so as to obtain M data and Y data. The data corresponding to eight addresses is generally used, but the data corresponding to six addresses is also used in this field.
Generally, the above-described color conversion data memory area is formed by a plurality of RAMs. One example of the conventional RAM is shown in FIG. 17. In this example, the RAM is a static RAM, and a memory cell is selected by two stages, that is, by a word line and a division word line.
The RAM 100 includes a plurality of memory arrays 101 (1st block through ath block) having the same cell configuration. In each of the memory arrays 101, “c” number of word lines WL are respectively connected to division word lines DWL via division word line selectors 102. Memory cells whose number is “b” are connected to each of the division word lines DWL. Each of the memory cells 103 (MC) corresponds to one bit. At each column, the memory cells 103 are connected to a pair of bit lines BL and BLB so as to be located between the pair of bit lines BL and BLB. One end of each of the bit lines BL and BLB are connected to a pre-charging circuit 104. The bit lines BL and BLB are connected to a pair of data lines DL and DLB via a column gate 105. Each pair of data lines DL and DLB are connected to a data input/output circuit 108 via a sense operational amplifier 106 and a write buffer 107.
In the RAM 100, data is read from the memory cells 103 of each memory array 101, and data is written in the memory cells 103 of each memory array 101. This reading/writing operation is performed based on an address signal and a control signal that are sent to a row decoder 109 and a column decoder 110 from an address input circuit 111 and an internal control circuit 112. In other words, the address input circuit 111 and the internal control circuit 112 send the address signal and the control signal to the row decoder 109 and the column decoder 110 based on an external signals indicated by CEB, WEB, and ADD[h:0] in FIG. 17. The opening/closing of column gates 105 is controlled by selection signals G[a-1:0] output from the column decoder 110. At the time of the operation, the selection signals G[0] through G[a-1] as gate signals are one-by-one input to the 1st memory array through the ath memory array, respectively. One of the “a” number of the gate signals is made to rise so that only one of the “a” number of the memory arrays can be selected.
One division word line DWL to which “b” number of memory cells 103 are connected forms one word in each memory array 101. Accordingly, the RAM having such a configuration has a capacity of: a×c(words)×b(bits).
In FIG. 17, ADD[h:0] is shown as an input terminal of the address input circuit 111 (“h” is equal to or larger than “2”). However, three types of addresses X[i:0], Y[j:0], and Z[k:0] may be used as address input terminals. In this case, the address X is decoded by the row decoder 109, and the addresses Y and Z are decoded by the column decoder 110.
When all of “i”, “j”, and “k” are “1”, “c” is “4”, and “a” is “16”. FIG. 18A shows one example of the address arrangement of the RAM having the storing area of “a×c” words. This RAM has respective blocks each of which forms one word. As shown in FIG. 18B, one block 115 corresponding to one word is configured so as to include one word line selector 102 and the division word line DWL having the “b” number of memory cells connected to this division word line DWL.
The addresses input from the address input terminals X[i:0], Y[j:0], and Z[k:0] are expressed by (z, y, x). In the case of simultaneously using the data corresponding to eight addresses that are made by adding “1” to one, two, and all of “x”, “y”, and “z” and that includes the base address (z, y, x) (refer to FIG. 16), the data corresponding to eight blocks indicated by “0” through “{circle around (7)}” of FIG. 18A is simultaneously required. In this example, (z, y, x)=(00, 00, 01) indicates Z[1]=Z[0]=0, Y[1]=Y[0]=0, and X[1]=X[0]=1.
However, in the case of the RAM having the configuration shown in FIG. 17, the eight specified addresses correspond to blocks that are adjacent to each other, as shown in FIG. 18A. Furthermore, in this case, each pair of bit lines BL and BLB is shared by the blocks. Accordingly, the data corresponding to the eight addresses cannot be read simultaneously by one cycle. As one example, in order to simultaneously use the data corresponding to the eight addresses, eight RAMs are used, at the time of writing, the same data is written in the same address of each of the eight RAMs, and at the time of reading, data is output from the respective different addresses of the respective RAMs, for example. However, in this case, the entire chip area becomes large.
As another example, in order to use the data corresponding to the eight addresses, eight other RAMs each of which has one eighth of capacity of the RAM shown in FIG. 18A, i.e., has the capacity of a×c=4×2, are used. In FIG. 19A, the blocks 115 of FIG. 18A that are specified by the X address, the Y address, and Z address are respectively distributed to the eight RAMs each of which has a capacity of a×c=4×2. That is, by this address distribution, the blocks 115 of the eight addresses that are accessed simultaneously are distributed to the eight RAMs, respectively. In this example, “0” to “{circle around (7)}” shown in FIG. 19A correspond to “0” to “{circle around (7)}” shown in FIG. 18A. In order to simultaneously access the eight addresses of the eight RAMs such as “0” to “{circle around (7)}” shown in FIG. 19A, a peripheral circuit external to the eight RAMs may decode the addresses, as shown in FIG. 19B.
With this configuration, it is possible to simultaneously use the data corresponding to the eight addresses without changing the total RAM capacity. However, in this case, the RAM is divided into eight block groups, so that each block group needs a specific control circuit. As a result, plural control circuits are used. In addition, a wiring area for the connection between the eight block groups and an external address decoder is required, so that the entire area becomes large.
Furthermore, in order to simultaneously access the eight addresses, “8×b” number of wires for transmitting and receiving data are required for the only input use, and this number of the wires for transmitting and receiving data increases by two times when taking into account the output use. Accordingly, the entire area becomes large.
In order to simultaneously access eight addresses, Japanese Laid-Open Patent Application No. 6-349268 discloses a semiconductor storing device that can perform one writing operation to simultaneously write data in a plurality of consecutive memory cells that belong to one row address and that are in an arbitrary range. Further, Japanese Laid-Open Patent Application No. 5-113928 discloses an image memory apparatus that converts an address, and can simultaneously access a plurality of memory cells either in the case of data of plural kinds of displaying elements corresponding to the same pixel or in the case of data of the same kind of displaying elements corresponding to plural pixels.
In these two prior techniques, it is possible to simultaneously access a plurality of addresses. However, the simultaneous access to a plurality of addresses is limited to one row address. Objects of these prior techniques are different from the object of the present invention which is to simultaneously access a plurality of addresses that are selected based on the base address (z, y, x).